产品概述
The ADN4664BRZ is a dual CMOS low voltage differential signalling (LVDS) Line Receiver offering data rates of over 400Mbps (200MHz) and ultralow power consumption. It features a flow-through pin-out for easy PCB layout and separation of input and output signals. The device accepts low voltage (310mV typical) differential input signals and converts them to a single-ended 3 V TTL/CMOS logic level. The ADN4664 and its companion driver, the ADN4663, offer a new solution to high speed, point-to-point data transmission and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).
- Flow-through pin-out simplifies PCB layout
- High impedance outputs on power-down
- Interoperable with existing 5V LVDS drivers
- Accepts small swing differential signal levels
- Supports open, short and terminated input failsafe
- 3mW Typically low power design
- 0V to -100mV Threshold region
- 100ps Channel-to-channel skew typical
- 2.5ns Maximum propagation delay
应用
通信与网络, 时钟与计时
产品信息
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- 差分
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- 9mA
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- -40°C
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- 85°C
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- 3V
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- 3.6V
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- SOIC
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- 8引脚
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- 400Mbps
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- LVDS
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- CMOS, TTL
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- 15kV
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- MSL 1 -无限制