SN65LVDS105PW .

产品概述

The SN65LVDS105PW is a LVDS Clock Fan-out Buffer for network routers. The differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling and switching speeds to transmit data at relatively long distances. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signalling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock/serial data stream.

• Electrically compatible with LVDS, PECL, LVPECL, LVTTL, SSTL or HSTL outputs with external networks
• Low-voltage differential signaling with typical output voltage of 350mV and a 100R load
• LVTTL levels are 5V tolerant
• Driver outputs are high-impedance when disabled or with VCC <1.5V
• 400MHz Clock frequency
• 2.2ns Typical propagation delay time

应用

时钟与计时, 无线, 通信与网络